The present invention relates to a programmable controller which performs high-speed pulse output to control a controlled apparatus for positioning control according to a user program.
FIG. 3 is a diagram showing the structure of a conventional programmable controller.
In FIG. 3, the reference numeral 1 denotes a central processing unit (which will be hereinafter referred to as a “CPU”) for controlling each section of the programmable controller, and the reference numeral 2 denotes a pulse generating section for generating a pulse string in a cycle set by the CPU 1.
FIGS. 4A and 4B are flowcharts showing the operation of the conventional programmable controller. FIG. 4A shows a main processing and FIG. 4B shows an interruption processing.
In the main processing shown in FIG. 4A, first of all, the CPU 1 sets an output pulse cycle of the pulse generating section 2 at Step S1 and sets a residual pulse number indicative of an output pulse number at Step S2. Then, an interrupt enable state for enabling interruption is set at Step S3 and pulse output is started at Step S4. At Step S5, pulse output for the residual pulse number is carried out. When the pulse output is completed, an interrupt disable state is set at Step S6. Thus, the main processing is ended.
Every time one pulse is output at the Step S5, the interruption processing shown in FIG. 4B is executed. At Step S11, one is subtracted from the residual pulse number. When the residual pulse number reaches zero, a processing of stopping the pulse output is carried out at Step S13. Thus, the interruption processing is ended. If the residual pulse number is not zero at the Step S12, the interruption processing is ended and the control is returned to the main processing. By the main processing, the pulse output at the Step S5 is executed successively.
The conventional programmable controller comprises a CPU 1 for controlling each section and a pulse generating section 2 for generating a pulse string having a cycle set by the CPU 1 as shown in FIG. 3, and is controlled by control means for executing an interruption processing for each pulse output as shown in FIGS. 4A and 4B. The control means sequentially subtracts one from the residual pulse number for each output pulse, and executes the processing of stopping the pulse when the residual pulse number reaches zero.
In the conventional art, the CPU 1 should execute an interruption processing for each pulse output. For example, in case where a pulse of 200 KHz is output, an interruption cycle is 5 μs. Therefore, it is necessary to use a high-speed CPU applicable to the interruption processing having a cycle of 5 μS. However, the CPU applicable to such a high-speed processing using a general one-chip microcomputer is expensive. As a result, the cost of a product is increased.